Timing circuits are used in digital circuits to generate and align clock signals. For example they are used to synthesize clocks at various frequencies in microprocessors and other computer circuits. They are also used to generate and recover bit clocks in data communication circuits. Most of these timing circuits take the form of a phase-locked loop (PLL) or a delay-locked loop (DLL). The design and analysis of these timing circuits is discussed in detail in Dally and Poulton, Digital Systems Engineering, Cambridge, 1998, pp. 428-447.
An example DLL is shown in FIG. 2. Input aclk is delayed by five inverters 121-125 generating five equally-spaced clock phases, bclk-fclk. The phase comparator 126 compares phases bclk and fclk and outputs control signals up and down to charge pump 127. The charge pump 127 transfers charge to or from capacitor 128 in response to the control signals to adjust the voltage on inverter supply line 129. By adjusting the inverter supply voltage, the phase comparator and charge pump act to bring bclk and fclk into phase. Once the DLL control loop has converged, bclk and fclk are in phase, and clocks bclk to eclk have equally spaced phases 90-degrees apart (and complemented for the odd phases).
As illustrated in FIG. 3, if fclk is slow, i.e., its phase lags that of bclk, the phase comparator 126 asserts control signal up from the rising edge of bclk to the rising edge of fclk. The up signal causes the charge pump 127 to transfer charge to capacitor 128, effectively pumping its voltage up. This voltage is buffered by voltage follower 130 to provide inverter supply voltage 129. The increase in the inverter supply voltage reduces the delay of inverters 121-125 which reduces the phase difference between bclk and fclk. After many cycles of small adjustments, the phases of bclk and fclk are aligned.
The situation when fclk is too fast is illustrated in FIG. 4. Here the phase comparator 126 asserts control signal down from the rising edge of fclk to the rising edge of bclk. In response to this signal, charge pump 127 transfers charge from capacitor 128 reducing the capacitor voltage. This increases the delay of the inverters 121-125 which slows fclk to bring it into phase with bclk.
In the past, phase comparators have been constructed using flip-flops (c.f., Dally and Poulton pp. 431-433 and p. 617), exclusive-OR gates (c.f., Dally and Poulton pp. 433-434 and pp. 615-617), and sequential logic circuits (c.f., Dally and Poulton pp. 434-436, pp. 459-460, and pp. 617-620). The waveforms in FIGS. 3 and 4 correspond to the output of a sequential phase-only comparator.
The logic diagram of a sequential phase-only comparator (described in Dally and Poulton pp. 459-460, and pp. 617-620) is shown in FIG. 5. This circuit compares the phase of bclk and fclk and generates a pulse on up with width proportional to the phase difference if bclk leads fclk. If fclk leads bclk a pulse is generated on down with width proportional to the phase difference.
When fclk and bclk are exactly aligned, this circuit generates small, equal pulses on both up and down. Generating pulses on both outputs when fclk and bclk are aligned is necessary to prevent a dead band in the phase comparator response at the point of zero phase difference. If no pulses were generated when fclk and bclk are aligned, there would be a range of phase difference about zero, a dead band, where the phase comparator would produce no output and hence would not be able to control the phase difference in the proper direction.
The circuit of FIG. 5 is an asynchronous sequential logic circuit that detects the rising edges of the clock signals. Gates 131 through 136 form a positive edge-triggered flip-flop that is set on the rising edge of bclk. Similarly gates 137 through 142 form a positive edge-triggered flip-flop that is set on the rising edge of fclk. After both rising edges have occurred, the output of gate 143 goes high resetting both flip flops. Thus, each output is high from the time its corresponding input rises until both outputs have gone high. The delays of the gates are adjusted to ensure that both outputs go high before gate 143 resets them, ensuring that there is no dead band in the phase response of the circuit.
A typical prior art charge pump is illustrated in FIG. 7. This circuit accepts up and down inputs from the phase comparator and sources or sinks charge to output capacitor 111. When input up is asserted it switches on FET 161 which enables current-source FET 104 to sink current from node 112. This current is mirrored by current-mirror FETs 105 and 110 to source current onto the output. The duration of the current pulse on the output, and hence the charge deposited on capacitor 111 is directly proportional to the width of the up pulse. When the down input is asserted it switches on FET 162 which enables current source FET 109 to directly sink current from output capacitor 111. The amount of charge removed from the capacitor is directly proportional to the width of the down pulse.